Field of the Disclosure
The present disclosure relates to a gate driving unit and a display device including the same, and more particularly, to a gate driving unit and a display device including the same that prevent deterioration in charge capability of a node of a dummy stage.
Discussion of the Related Art
With rapid development of information technologies, various types of display devices for displaying images have been required. Recently, flat panel display (FPD) devices such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, and organic light emitting diode display (OLED) devices have been widely developed and applied to various fields.
These display devices include drivers for driving the display devices. The driver includes a gate driving unit for sequentially supplying gate pulses to gate lines and a data driving unit for supplying video signals (i.e., data voltages) to data lines.
Particularly, the gate driving unit includes a plurality of stages for sequentially generating gate pulses.
FIG. 1 is a view showing stages of a gate driving unit according to the related art. FIG. 2 is a timing chart showing input signals to a dummy stage of FIG. 1, an (n+1)th Q node voltage of the dummy stage, an (n+1)th QB node voltage of the dummy stage, and a dummy pulse outputted from the dummy stage.
In FIG. 1 and FIG. 2, the gate driving unit according to the related art includes first to nth (n is an integer larger than 2) stages and a dummy stage. The first to nth stages sequentially output first to nth gate pulses Vout1 to Vout(n), respectively, according to a start signal Vst. The dummy stage receives the nth gate pulse Vout(n) and outputs a dummy pulse Vout(n+1).
More specifically, the first stage receives the start signal Vst and outputs the first gate pulse Vout1 by using a clock signal Clk inputted to the first stage. At this time, the first gate pulse Vout1 outputted from the first stage is inputted to the next stage, thereby starting the next stage.
Next, the nth stage receives the gate pulse outputted from the previous stage and outputs the nth gate pulse Vout(n) by using the clock signal Clk inputted to the nth stage. At this time, the nth gate pulse Vout(n) outputted from the nth stage is inputted to the previous stage, thereby resetting the previous stage, and is inputted to the dummy stage, thereby starting the dummy stage.
Next, the dummy stage receives the nth gate pulse Vout(n) outputted from the nth stage and outputs the dummy pulse Vout(n+1) by using the clock signal Clk inputted to the dummy stage. At this time, the dummy pulse Vout(n+1) outputted from the dummy stage is inputted to the nth stage, thereby resetting the nth stage.
In addition, the dummy stage receives the start signal Vst and is reset.
Meanwhile, every time a frame ends, the first to nth stages and the dummy stage receive a reset signal Rst to prepare a next frame.
The reset signal Rst, the start signal Vst and the clock signal Clk are inputted to the gate driving unit during one frame. The reset signal Rst for resetting the previous frame is first inputted and then the start signal Vst for starting the present frame is inputted for the frame. In addition, the clock signal Clk is periodically inputted with a predetermined interval.
At this time, the first clock signal Clk of the present frame is inputted after the start signal Vst is inputted.
Hereinafter, a process of outputting the dummy pulse Vout(n+1) from the dummy stage will be described.
The nth gate pulse Vout(n) outputted from the nth stage is inputted to the dummy stage, and an (n+1)th Q node (Q(n+1)) of the dummy stage is charged to have a high level voltage Vdd. The dummy pulse Vout(n+1) corresponding to the clock signal Clk is outputted from the dummy stage by the high level voltage Vdd of the (n+1)th Q node (Q(n+1)).
In the meantime, threshold voltages of transistors included in the dummy stage are shifted toward a (+) direction in proportion to an accumulated amount of a positive bias stress (PBTS) or shifted toward a (−) direction in proportion to an accumulated amount of a negative bias stress (NBTS).
Especially, the positive bias stress PBTS is accumulated at gate electrodes of the transistors switched corresponding to a voltage of an (n+1)th QB node (QB(n+1)). The positive bias stress PBTS proportionally increases as driving time passes, and the corresponding transistors are degraded.
Since the transistors switched corresponding to the voltage of the (n+1)th QB node QB(n+1) are degraded by the positive bias stress PBTS, an ability of discharging the charged (n+1)th Q node Q(n+1) is lowered, and an ability of charging the (n+1)th QB node QB(n+1) is lowered.
Namely, the charged (n+1)th Q node (Q(n+1)) of the dummy stage is discharged by the start signal Vst, and the (n+1)th QB node QB(n+1) is charged by the reset signal Rst faster than the start signal Vst. Since the charged (n+1)th Q node Q(n+1) is not completely discharged, the ability of charging the (n+1)th QB node (QB(n+1)) is lowered.
Thus, the (n+1)th QB node (QB(n+1)) is not sufficiently charged, and the charged (n+1)th QB node (QB(n+1)) is easily discharged. When the charged (n+1)th QB node (QB(n+1)) is discharged, the (n+1)th Q node (Q(n+1)) is recharged corresponding to the clock signal Clk.
In addition, the dummy pulse Vout(n+1) is outputted again due to a voltage of the recharged (n+1)th Q node (Q(n+1)).
As a result, the dummy pulse Vout(n+1) is outputted from the dummy stage twice every frame. The nth stage is reset two times by the twice outputted dummy pulse Vout(n+1), and this causes a problem of lowering an image quality of the display device.